This invention relates to the fabrication of semiconductor devices and, in particular, to field effect transistors (FET's) intended for operation at microwave and millimeter frequencies.
The electrical performance of a semiconductor device is dependent upon the structural configuration and, in particular, on the ability of the structure to reduce elemental parasitics, such as series resistance, shunt capacitance and series inductance. The reliability of a device is dependent upon the metallurgical techniques used to provide the junction passivation and to produce the ohmic and Schottky contacts.
Although the last decade has seen good progress in the development and fabrication of FET devices that provide excellent performance and reliability, further progress in these areas is a definite requirement, especially for devices intended for applications in the millimeter frequency ranges.
The basic structure of a conventional FET, shown in FIG. 1, is fabricated upon a semi-insulating substrate 101 and an active, epitaxial N-layer 102. Such substrates are typically made of gallium arsenide. FIG. 1 shows the device to further comprise a source 103, a gate 104, a drain 105, a source to gate length (Lsg) 106, a gate length (Lg) 107, a gate to drain length (Lgd) 108, and a depletion layer 109 located beneath the gate. Contacts for the source 103, gate 104 and drain 105 are made to the active N-layer to control the flow of current between the source and drain. The ohmic contacts are made by sinter alloying a metallic film composed of nickel-germanium gold to the active layer. The nickel-germanium gold, referred to herein as simply germanium gold or Ni-GeAu, usually ranges between 500 and 1000 Angstroms in thickness. The germanium gold film is typically composed of 12 percent germanium and 88 percent gold. Using this contact composition, a contact resistivity ranging between 3 and 5.times.10 to the -6th power ohm-centimeter has been achieved. In this structure, the input series resistance can be in the 3 to 5 ohms range if the active N-layer's concentration ranges between 1 and 3.times.10 to the 17 power per cubic centimeter and the source ohmic contact is positioned within 1 micron of the gate edge.
For this device configuration, the minimum input source series resistance that can be achieved is limited by the finite source-to-gate length (Lsg) of the conducting channel. For some low noise and low power application this channel length has been reduced to 0.5 microns. However, the reliability and yield of these devices is poor since gold and nickel can easily inter-diffuse with GaAs and eventually diffuse into the active conducting channel, resulting in device performance degradation and ultimately catastrophic failure. An additional limitation of this structure is the effective length of the channel under the gate which is much greater than the metallurgical gate length, resulting in greater effective source to gate capacitance and consequently a lower maximum frequency of oscillation. Furthermore, the conducting channel is fully exposed to the ambient and to contaminants that contribute to poor RF performance and reliability.
To improve device reliability, various dielectric layers, such as SiO.sub.2 and Si.sub.3 N.sub.4, have been used to passivate the exposed conducting channel. SiO.sub.2 is known to be ineffective as a passivation for sodium ions, the most notably troublesome contaminant. On the other hand, Si.sub.3 N.sub.4 is an effective passivation only for sodium ions. In order to provide a complete passivation both SiO.sub.2 and Si.sub.3 N.sub.4 must be used.
For conventional FET devices, the use of these dielectrics often increase the parasitic capacitance between the source and gate (Csg), between gate and drain (Cgd), and between source and drain (Csd). These added parasitic capacitances effectively limit the efficient operation of conventional FETs to well below 20 GHz.
To improve FET performance, other configurations, such as those shown in FIGS. 2 and 3, have been developed. As can be seen in these Figures, the improved FET structures are similar to the conventional structure of FIG. 1, with the exception that a first epitaxial N+ layer 201 has been added at the surface of the semi-insulating substrate beneath the source, and a second epitaxial N+ layer 202 has been added beneath the drain. FIG. 3 also differes from FIG. 1 in that the gate is placed in a recess 301 in the N layer.
Unfortunately, the quality of the epitaxial layers in these structures are difficult to evaluate. In addition, the fabrication steps are more complex and result in poor device yield as well as poor characteristic uniformity.
On the other hand, these devices do provide some advantages over the basic FET structure shown in FIG. 1. These advantages include the ability to achieve a lower contact series resistance, lower channel resistance and higher voltage breakdown. The lower contact resistance is achieved by using a highly doped N+ layer with a doping concentration of approximately 2.times.10 to the 18th power per cubic centimeter. The lower channel resistance is achieved by using a thicker active N-layer outside the gate region where a recessed gate is employed as shown in FIG. 3. A higher voltage breakdown is achieved by providing a greater separation between the gate and drain. In addition, the N+ layer can be extended close to the gate to further reduce the parasitic series resistance of the source and drain.
Although some relative minor improvements in electrical performance are attained by the structures shown in FIGS. 2 and 3, there is no appreciable improvement in reliability over the basic FET of FIG. 1. These devices are similar to the basic FET structure in that the channel is exposed to the ambient and contaminants, the ohmic contact to the source is still within one micron of the gate, and the effective gate length is greater than the metallurgical length of the gate.
FIG. 4 shows a FET structure which was developed for low power, high speed logic applications. This device is similar to the device of FIG. 1, with the exception that there is a first N+ layer 401 under the source and a second N+ layer 402 under the drain. The N+ layers 401 and 402 differ from the N+ layers 201 and 202, shown in FIGS. 2 and 3, in that layers 401 and 402 extend up to the gate region rather than remaining confined to the areas immediately below the source and drain, and layers 401 and 402 occupy the area which is occupied by the N layer in FIGS. 2 and 3, except for one small segment which lies directly below the gate.
For low power, high speed logic devices, the required voltage breakdown at 10 uA is typically in the 3 to 5 voltage range. This structure makes use of ion implantation to implant the N+ layer into a semi-insulating substrate. To achieve a very low series resistance, the gate is formed prior to the ion implantation and acts as a mask during this process. Through the use of this technique, the edge of the N+ layers (source and drain) are colinear with the edge of the gate and thereby providing the desired lower series resistance. Ohmic contact of Ni-GeAu are then formed on the implanted N+ layers. Although the series resistance of this device is drastically reduced when compared to the devices of FIGS. 1 to 3, the voltage breakdown and the reliability are also reduced. The voltage breakdown that can be achieved depends upon the carrier concentration of the N+ layers and on the separation between the edges of the N+ layers and the gate. If the N+ layers are doped with a concentration of 10 to the 19th power per cubic centimeter, the expected voltage breakdown at 10 uA is well below 1 volt, making this device unreliable and difficult to fabricate. There is an additional factor which detracts from the reliability of this device. Following the ion implantation process, the wafer must be annealed at about 900 C. At this temperature, the gate metal tends to inter-diffuse with the N+ layer, about its edges, to form an ohmic contact or a short circuit.
The structure of FIG. 5, generally referred to as a permeable base transistor (PBT), is a "normally-off" device which was developed to extend the operating frequency range of FET's into the millimeter region. This device comprises an N+ layer 501, an N layer 502, a source 503, a gate 504, a drain 505 and a depletion layer 506. This Figure is a cross sectional view, showing the device to be formed of a series of layers. The arrangement of these layers beginning with the lowest layer is as follows: the source 503, the N+ layer 501, the N layer 502, the gate 504, a continuation of the N layer 502 and the drain 505. The gate is a thin layer which passes through the N layer and is divided into a series of fingers, such as finger 504A. The fingers are separated by a series of depletion layers, such as depletion layer 506.
The carrier doping concentration of this N-layer is about 1.times.10 to the 16th power per cubic centimeter in order to fully deplete the region between adjacent gate fingers at zero bias. In particular, the dimension d 507 is made less than the width of the depletion layer at zero volt bias. The thickness of the gate finger Lg 508, which is also the gate length, can be less than 500 Angstroms. Theoretically, for a doping concentration in the N layer of 1.times.10 to the 16th power per cubic centimeter, d equal to 1000 Angstroms, a distance from the gate to the drain (.times.510) of 0.6 um, a distance from the gate to the source (y 509) of 0.4 um and an Lg of 200 Angstroms, the calculated power delay product is nearly 1.times.10 to the minus 15th power joules, the maximum unity gain frequency is in excess of 200 GHz, and the minimum frequency of oscillation is nearly 1000 GHz.
The fabrication of this structure is extremely difficult. In particular, it requires the growth of a single crystal epitaxial layer at the edges and over the metal fingers of the gate. To achieve short gate lengths, the gate metal must be made very thin, increasing the gate resistance to an intolerable high value. To achieve a fully depleted layer, the value of the carrier concentration is reduced by an order of magnitude from 1.times.10 to the 17th power per cubic centimeter for a conventional FET to to 1.times.10 to the 16th power per cubic centimeter, producing an increase in the resistivity of the epilayer.
Although the PBT structure has been fabricated, the experimental results to date have not been encouraging. The best performance obtained with these devices thus far only approaches that achieved with conventional devices at frequencies well below 20 GHz.
The goal in the development of the above conventional and PBT FET structures was to increase the maximum oscillating frequency, lower the noise figures where the application was low noise amplifiers, increase the output power where the application was power amplifiers, and increase the switching speed where the application was gigabit logic circuitry. At the present time, the predicted maximum frequency of oscillation for conventional devices is 120 to 140 GHz. This limitation is attributed to the finite parasitic series resistance of the N-layer beneath the source, and the length of the depletion layer beneath the gate, which is larger than the physical length of the gate material. This makes the effective gate capacitance greater than that calculated from the physical dimensions of the gate and accordingly limits the operation of the device to lower frequencies.
The cross-section of a conventional FET device and its equivalent electrical circuits are shown in FIGS. 6A and 6B, respectively. This device comprises a semi-insulating layer 101, an N layer 102, a source 103, a gate 104 and a drain 105. The corresponding equivalent circuit comprises a gate resistance Rg 601, a source resistance Rs 602, an intrinsic channel resistance Ri 603, a drain to source resistance Rds 604, a drain resistance Rd 605, a source to gate capacitance Csg 606, a gate to drain capacitance Cgd 607, a source to drain capacitance Csd 608, and a current generator eg-gm 609, which produces a current equal to the gate voltage (eg) multiplied by the transconductance (gm). For this circuit, the maximum frequency of oscillation fm is given by: ##EQU1## where the frequency at unity gain f.sub.T is given by ##EQU2## and gm is the transconductance ##EQU3## EQU and EQU .tau..sub.3 =2.pi.Rg C.sub.dg
As indicated in the above equations, to achieve a high maximum frequency of oscillation, it is necessary to maximize f.sub..tau.. This is realized by decreasing the gate to source capacitance (Cgs), the gate to drain capacitance (Cgd), the parasitic source resistance (Rs), the gate resistance (Rg), the intrinsic channel resistance (Ri) and by increasing the transconductance (gm).
The value of Rs generally cannot be reduced below 1 ohm when using conventional FET structures designed for use in low noise or power application. Rs and Ri can be somewhat reduced by increasing the carrier concentration in the active N-layer, however, this results in the gate to drain voltage breakdown also being reduced.